Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

In this paper, experiments are conducted in order to quantitatively evaluate the tradeoffs between design complexity and area overhead, reconfiguration flexibility, and reconfiguration latency of two reconfiguration interfaces, i.e. SelectMAP and JTAG. The results show that the SelectMAP interface is highly suitable when reconfiguration latency needs to be kept to a minimum at the expense of a large area overhead and more rigid area control. On the other hand, the JTAG interface is preferable if significant control over the placement of reconfigurable modules in the reconfigurable fabric of the FPGA chip is desired and/or more flexible area management is required. The JTAG design consumes a factor of 3 to 7 times fewer logic resources and a third of the device pins, but can incur reconfiguration latency up to 40 times longer than the SelectMAP design.